FounderFiles · N°019
Andrew Feldman.
The systems architect who spent two decades arguing that interconnect, not raw compute, is the real limiter at extreme scale — and built the largest chip in history to prove it.
Wafer-Scale vs. Scale-Out Clusters
Andrew Feldman has spent nearly two decades making one consistent argument: at extreme scale, the interconnect and memory bandwidth limitations of traditional GPU clusters become first-order constraints. His solution is radical — build one enormous monolithic chip instead of networking thousands of smaller ones.
This is the core of Cerebras’ Wafer-Scale Engine thesis. While the industry doubled down on scale-out clusters, Feldman bet that a single, massive chip with enormous on-chip SRAM and bandwidth could bypass many of the fundamental bottlenecks that appear when coordinating tens of thousands of GPUs.
“The biggest constraint on training bigger models may no longer be the chip — it may be the wires between the chips.”
Power, Thermals, and Manufacturing
Wafer-scale computing concentrates enormous challenges into one device. Power delivery, cooling, and yield management become dramatically harder. Cerebras engineered a sophisticated defect-tolerant architecture with 70,000 redundant cores and dynamic routing to achieve ~93% active silicon utilization across a full 300mm wafer — something previously considered economically impossible.
The result is a chip with 21 PB/s of on-wafer memory bandwidth, representing roughly a 7,000× advantage over a discrete H100 in memory bandwidth.
The Developer Experience Friction
Even the most elegant hardware architecture struggles if moving models onto it is painful. Feldman has been direct about the software and ecosystem challenges of introducing a new architecture into a CUDA-dominated world. The Cerebras stack requires Ahead-of-Time compilation and static graphs, creating real friction for researchers used to dynamic PyTorch workflows.
The long-term success of wafer-scale computing depends as much on closing this developer experience gap as on raw silicon performance.
Two Decades of Systems Thinking
Feldman’s conviction didn’t appear overnight. His previous company, SeaMicro (acquired by AMD), was already focused on dense, efficient compute systems and innovative interconnect fabrics. The through-line from SeaMicro to Cerebras is a consistent focus on systems-level problems rather than chasing peak single-chip performance in isolation.
Andrew Feldman on wafer-scale computing
I-Beam Theorist
Drives one domain to maximal depth and lets the world reorganize around the result; commercialization is downstream, optional, or never.
- Credential Path
- Practitioner
- Abstraction
- Top Down
- Exit Horizon
- Deferred
- Moat Instinct
- Product Primitive
- Capital Posture
- Venture
- SeaMicro team
- hardware systems architects
- long-horizon chip designers
A small reasoning persona distilled from this file. Inject it into a chat or deep-research context to assess a business problem the way Feldman would.
Reason as Andrew Feldman. When given a scaling or systems problem at extreme AI size, first ask whether the implicit assumption is "more chips + better network" and whether that assumption is the actual limiter. Propose collapsing the interconnect problem into the silicon itself. Emphasize long-term architectural conviction over short-term cluster wins. Audit whether a proposed solution treats the network as a first-class citizen or as something to be engineered out of existence.
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"What is the real bottleneck when you scale AI training to the largest possible systems?",
"If the network is the problem, why keep scaling the network instead of removing it?",
"How do you make a chip so large that traditional manufacturi
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